1. Field of Invention
The present invention generally relates to dynamic random access memory (DRAM) apparatus, and more particularly to DRAM apparatus constructed by multi-layer chips.
2. Description of Prior Art
Along with the rapid development of science and technology at the present, semiconductor memories are widely used in electrical apparatus. For storing a great quantity of data, dynamic random access memory (DRAM) (such as synchronous dynamic random access memory (SDRAM)) is a most popular solution.
In a memory cell of a DRAM, to avoid a charge loss rapidly in a storage capacitor of the memory cell during a time period is a big issue when a minimum size of the semiconductor process is reduced. Please notice here, when the minimum size of the semiconductor process is reduced, the chip size of the DRAM is reduced, too. It can be realized that, area of the storage capacitor of the memory cell must be reduced, a capacitance provided by the storage capacitor is reduced, and a charge amount of the storage capacitor is reduced correspondingly. That is, the reliability of the memory cell is reduced. On the other hand, a charge loss of the storage capacitor may be increased caused by a high temperature processing for the size of the storage capacitor is reduced, and the reliability of the memory cell is reduced accordingly, too.